Nonvolatile memory devices, such as flash memory devices, are memory devices that can store information even when not powered. A flash memory device stores information in a charge storage layer that is separated from a “control gate.” A voltage is applied to the control gate to program and erase the memory device by causing electrons to be stored in and discharged from the charge storage layer.
To reduce the dimensions of nonvolatile memory devices, the use of localized charge storage is being investigated and commercialized as a replacement for the more established contiguous floating gate technology. Localized charge storage approaches include the use of nitride films, semiconductor quantum dots, and metallic quantum dots. Localized charge storage may provide advantages over contiguous floating gate technology in several areas. For example, localized storage may provide greater immunity to cell-to-cell coupling, improved data retention, and allow further size scaling of the tunnel oxide layer.
For some types of localized charge storage memory devices, the charging and discharging of the charge storage layer is accomplished by electron (or hole) tunneling. Conventional memory cell technology includes gate electrodes and silicon channels with sharp corners. Such sharp corners can create locally enhanced electric fields and, consequently, spatial variations in the tunneling rate during charging and/or discharging of the memory device. Such variations in tunneling rate across the memory cell may be particularly problematic in memory devices that utilize localized charge storage approaches.
For example, locally increased tunneling rates may be detrimental during the cell erase process. In the erase process, a negative voltage is applied to the control gate to induce electrons to tunnel out of the charge storage layer. Due to the sharp corners of the gate electrode, however, the local electric field may be enhanced sufficiently such that electrons tunnel into the charge storage layer from the control gate at the cell edges. Consequently, during the erase process, electrons may be added at the edges of the cell as they are being removed from the center of the cell. The electrons thus stored at the edges of the cell cannot easily be removed from the charge storage layer because they are in fact caused by the erase procedure.
In view of these problems, it would be advantageous to reduce spatial variations in the tunneling rate across the memory cell, particularly for nonvolatile memory devices that store charge in discrete or localized regions within the charge storage layer.